1. Technical Field
The present disclosure relates to semiconductor devices and methods of fabricating the same and, more particularly, to a contact structure of semiconductor devices and methods of fabricating the same.
2. Discussion of Related Art
Generally, interconnections of semiconductor devices may be formed in a stacking-structure, which is advantageous to high-intensity devices. Interlayer dielectric layers are formed between multi-layer interconnections, which are stacked vertically. Each interlayer dielectric layer insulates corresponding lower and upper interconnections. The lower and upper interconnections may be electrically connected to each other depending on the application. The lower and upper interconnections are electrically connected to each other using a contact technique, in which a contact hole penetrating the interlayer dielectric layer is disposed between the lower and upper interconnections. A contact plug or a portion of the upper interconnection may be filled in the contact hole.
As semiconductor devices become more highly integrated, the line width of interconnections and the diameter of contact holes are reduced. Therefore, operation speeds of semiconductor devices are decreased due to increasing resistances of the interconnections or a contact resistance between the lower and upper interconnections. Presently, there is much research being conducted to solve theses problems.
Aluminum is commonly used to form interconnects. Recently, copper interconnections have been suggested to reduce resistances of the interconnections because they have a lower resistivity value in comparison with aluminum interconnections.
FIG. 1 through FIG. 3 are cross-sectional views illustrating a method for fabricating semiconductor devices having a conventional copper interconnection.
Referring to FIG. 1, a lower interlayer dielectric layer 2 is formed on a semiconductor substrate 1. A lower interconnection 3 is formed in the lower interlayer dielectric layer 2. The lower interlayer dielectric layer 2 is formed of silicon oxide and the lower interconnection 3 is formed of copper. The lower interconnection 3 is formed in a groove in the lower interlayer dielectric layer 2. A barrier layer (not shown) can be disposed between the lower interconnection 3 and the lower interlayer dielectric layer 2. A silicon nitride layer 4 and an upper interlayer dielectric layer 5 are sequentially formed on the entire surface of the semiconductor substrate 1 including the lower interconnection 3.
The upper interlayer dielectric layer 5 and the silicon nitride layer 4 are successively patterned to form a contact hole 6 exposing a predetermined region of the lower interconnection 3. A high-resistance copper compound 7 may be formed on the lower interconnection 3 exposed at the contact hole 6. The high-resistance copper compound 7 can be formed by native oxidizing the exposed lower interconnection 3. Accordingly, the high-resistance copper compound 7 can be isotropically formed from a surface of the lower interconnection 3 exposed at the contact hole 6. As a result, the top area of the high-resistance copper compound 7 is larger than an area exposed by the contact hole 6. Furthermore, the high-resistance copper compound 7 may further include an etching by-product. The etching by-product may be formed during formation of the contact hole 6.
Referring to FIG. 2 and FIG. 3, contact resistance is increased due to the high-resistance copper compound 7. Therefore, the high-resistance copper compound 7 is completely removed by performing a post-treatment process at the semiconductor substrate 1 including the high-resistance copper compound 7. As a result, a concave region 8 is formed in position of the high-resistance copper compound 7. Depending on the configuration of the high-resistance copper compound 7, edges of the concave region 8 can be placed under the silicon nitride layer 4.
A contact plug 9 filling the contact hole 6 is formed. The contact plug 9 may be formed of a stacked barrier layer (not shown) and a copper layer. At this time, a void 10 may occur at the edge of the concave region 8 placed under the silicon nitride layer 4. Therefore, the contact plug 9 may not completely fill the concave region 8.
Consequently, resistance between the contact plug 9 and the lower interconnection 3 is increased due to the void 10. Furthermore, reliability of semiconductor devices having the void 10 is degraded.